Classic RISC pipeline: Difference between revisions

Revision as of 18:55, 23 January 2023

Revision as of 10:17, 28 August 2023

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{{Short description|Instruction pipeline}}

{{Use American English|date = March 2019}}

{{NoMore footnotes|date=December 2012}}

In the [[history of computing hardware|history of computer hardware]], some early [[reduced instruction set computer]] [[central processing unit]]s (RISC CPUs) used a very similar architectural solution, now called a '''classic RISC pipeline'''. Those CPUs were: [[MIPS architecture|MIPS]], [[SPARC]], Motorola [[Motorola 88000|88000]], and later the notional CPU [[DLX]] invented for education.

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* Register-Register Operation (Single-cycle latency): Add, subtract, compare, and logical operations. During the execute stage, the two arguments were fed to a simple ALU, which generated the result by the end of the execute stage.

* Memory Reference (Two-cycle latency). All loads from memory. During the execute stage, the ALU added the two arguments (a register and a constant offset) to produce a virtual address by the end of the cycle.

*[[Cycles per instruction |Multi-cycle Instructions]] (Many cycle latency). Integer multiply and divide and all [[floating-point]] operations. During the execute stage, the operands to these operations were fed to the multi-cycle multiply/divide unit. The rest of the pipeline was free to continue execution while the multiply/divide unit did its work. To avoid complicating the writeback stage and issue logic, multicycle instruction wrote their results to a separate set of registers.

===Memory access===

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During this stage, both single cycle and two cycle instructions write their results into the register file.

Note that two different stages are accessing the register file at the same time -- thetime—the decode stage is reading two source registers, at the same time that the writeback stage is writing a previous instruction's destination register.

On real silicon, this can be a hazard (see below for more on hazards). That is because one of the source registers being read in decode might be the same as the destination register being written in writeback. When that happens, then the same memory cells in the register file are being both read and written the same time. On silicon, many implementations of memory cells will not operate correctly when read and written at the same time.

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But the programmer, especially if programming in a language supporting [[large numbers|large integers]] (e.g. [[Lisp (programming language)|Lisp]] or [[Scheme (programming language)|Scheme]]), may not want wrapping arithmetic. Some architectures (e.g. MIPS), define special addition operations that branch to special locations on overflow, rather than wrapping the result. Software at the target ___location is responsible for fixing the problem. This special branch is called an exception. Exceptions differ from regular branches in that the target address is not specified by the instruction itself, and the branch decision is dependent on the outcome of the instruction.

The most common kind of software-visible exception on one of the classic RISC machines is a [[Translation_lookaside_bufferTranslation lookaside buffer#TLB-miss_handlingmiss handling|''TLB miss'']].

Exceptions are different from branches and jumps, because those other control flow changes are resolved in the decode stage. Exceptions are resolved in the writeback stage. When an exception is detected, the following instructions (earlier in the pipeline) are marked as invalid, and as they flow to the end of the pipe their results are discarded. The program counter is set to the address of a special exception handler, and special registers are written with the exception ___location and cause.

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== References ==

{{Reflist}}

{{refbegin}}

* {{cite book |first1=John L. |last1=Hennessy |first2=David A. |last2=Patterson |title=Computer Architecture, A Quantitative Approach |publisher=Morgan Kaufmann |edition=5th |year=2011 |isbn=978-0123838728 |url=https://books.google.com/books?id=v3-1hVwHnHwC}}

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{{CPU technologies}}

[[fa : خط لوله کلاسیک]]

[[Category:Instruction processing|Pipeline Classic RISC]]

[[Category:Superscalar microprocessors]]

[[fa : خط لوله کلاسیک]]