Depletion-load NMOS logic: Difference between revisions

Revision as of 14:59, 14 September 2023

Revision as of 15:00, 14 September 2023

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==Compared to CMOS==

Compared to static CMOS, all variants of NMOS (and PMOS) are relatively power hungry in steady state. This is because they rely on load transistors working as [[resistor]]s, where the [[quiescent current]] determines the maximum possible load at the output as well as the speed of the gate (i.e. with other factors constant). This contrasts to the power consumption characteristics of ''static'' CMOS circuits, which is due only to the transient power draw when the output state is changed and the p- and n-transistors thereby briefly conduct at the same time. However, this is a simplified view, and a more complete picture has to also include the fact that even purely static CMOS circuits have significant leakage in modern tiny geometries, as well as the fact that modern CMOS chips often contain [[dynamic logic (digital logicelectronics)|dynamic]] and/or [[domino logic]] with a certain amount of ''pseudo nMOS'' circuitry.<ref>''Pseudo nMOS means that an enhancement-mode p-channel transistor with grounded gate is used in place of the depletion-mode n-channel transistor. See http://eia.udg.es/~forest/VLSI/lect.10.pdf''</ref>

== Evolution from preceding NMOS types ==