Bit-serial architecture: Difference between revisions

Revision as of 12:36, 24 September 2023

Revision as of 12:45, 24 September 2023

Line 9:

Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref name="Denyer_1995"/>

The [[HP Nut]] processor used in many [[Hewlett-Packard calculator]]s operated bit-serially.<ref>https: name="Smith_2023"//web.archive.org/web/20230810144726/https://www.hpmuseum.org/forum/thread-20281.html</ref>

Often, N serial processors will take less [[FPGA]] area and have a higher total performance than a single N-bit parallel processor.<ref name="Andraka"/>

Line 26:

{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=[[Addison-Wesley]] |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books?id=EklTAAAAMAAJ}}</ref>

<ref name="Andraka">{{cite web |title=Building a High Performance Bit Serial Processor in an FPGA |author-first=Raymond J. |author-last=Andraka. |url=http://www.fpga-guru.com/files/supercn.pdf}}</ref>

<ref name="Smith_2023">{{cite web |title=HP-15C CE woes: 1 bug, 2 limitations, 3 questions |author-first=Eric L. "brouhaha" |author-last=Smith |date=2023-08-09 |work=MoHPC - The Museum of HP Calculators |url=https://www.hpmuseum.org/forum/thread-20281.html |access-date=2023-09-24 |url-status=live |archive-url=https://web.archive.org/web/20230810144726/https://www.hpmuseum.org/forum/thread-20281.html |archive-date=2023-08-10}}</ref>

}}