Intel 5-level paging: Difference between revisions

Revision as of 10:46, 19 September 2023

Revision as of 10:21, 4 October 2023

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== Technology ==

[[x86-64]] processors without this feature use a four-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|2806}} A similar situation arose when the 32 bit [[IA-32]] processors used two levels, allowing up to four [[gigabyte|GB]] of memory (both virtual and physical). To support more than 4&nbsp;GB of [[RAM]], an additional mode of address translation called [[Physical Address Extension]] (PAE) was defined, involving a third level.<ref>{{Cite web|url=https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=docs.microsoft.com|date=June 2017 |language=en-us|access-date=2018-04-26}}</ref> This was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref name="x86-software-developers-manual" />{{Rp|2799}} Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, the processor operates with four paging levels.

As adding another page table multiplies the address space by 512, the virtual limit has increased from 256&nbsp;TB to 128&nbsp;PB. An extra nine bits of the virtual address index the new table, so while formerly bits&nbsp;0 through&nbsp;47 were in use, now bits&nbsp;0 through&nbsp;56 are in use.