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ZISC is a hardware implementation of [[Kohonen network]]s (artificial neural networks) allowing massively parallel processing of very simple data (0 or 1). This hardware implementation was invented by Guy Paillet<ref name="Neuron circuit">{{Cite web|url=https://patents.google.com/patent/US5621863|title = Neuron circuit}}</ref> and Pascal Tannhof (IBM),<ref>{{cite web |url=https://www.researchgate.net/profile/Pascal-Tannhof |title=Profile: Pascal Tannhof |website=[[ResearchGate]]}}</ref><ref name="Neuron circuit"/> developed in cooperation with the IBM chip factory of [[Essonnes]], in France, and was commercialized by IBM.
The ZISC architecture alleviates the [[memory bottleneck]]{{clarify|date=December 2016}} by blending pattern memory with pattern learning and recognition logic.{{how|date=December 2016}} Their massively [[parallel computing]] solves the {{Clarify|text="[[Winner-take-all in action selection|winner takes all problem in action selection]]"|post-text=from [[Winner-take-all (computing)|Winner-takes-all]] problem in [[Artificial neural network|Neural Network]]s|reason=Per [https://web.archive.org/web/20170101001452/https://pdfs.semanticscholar.org/1e0c/54bd88223e009997a04dcd2a0f3fa0af3848.pdf source], [[Winner-take-all (computing)|Winner-takes-all]] is defined as a different principle from [[Winner-take-all in action selection]], but both are relevant to [[Artificial neural network|Neural Network]]s|date=December 2016}} by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.<ref name="Gigaom"/>
===Applications and controversy===
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