Content deleted Content added
No edit summary Tags: Visual edit Mobile edit Mobile web edit |
→Algorithm: Added example and its images. needs copyedit. |
||
Line 30:
[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the ''x'' axis. Approximation value on the ''y'' axis.|right]]
'''Example 1:''' The ten steps to converting an analog input to 10 bit digital, using successive approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.
The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625, 0.0048828125. All of these add up to 4.9951171875, meaning binary 1111111111, or one LSB less than 5.
When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the end result, a binary number representing the analog input, is found.
'''Example 2:''' The working of a 4-bit successive approximation ADC is illustrated below. The MSB is initially set to 1 whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on {{math|1=2<sup>''n''</sup>}} volts range can be expressed as an algorithm:
# Initialize register with MSB set to 1 and all other values set to zero.
# In n-th clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)-th digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n-th digit from left is set to zero and the next digit is set to 1. For N bit DAC, there exists N such clock cycles excluding the initial state.
{{Multiple image|
<!-- Layout parameters -->
| align = center
| direction = horizontal
<!-- Header -->
| header_align = center
| header = Working of Successive Approximation ADC
<!--image 1-->
| image1 = Successive-approximation ADC example Setup.svg
| width1 = 330
| caption1 = Successive-approximation ADC example setup where output values of the ADC are arranged in a grid, vertical axis corresponding to voltage. It is a 4-bit ADC that measures input voltages from 0V to 15V.
<!--image 2-->
| image2 = Successive-approximation ADC example working value 1.svg
| width2 = 290
| caption2 = Previously established successive-approximation ADC example setup where an input voltage of 10.4V is provided, is illustrated in the figure.
<!--image 3-->
| image3 = Successive-approximation ADC example working value 2.svg
| width3 = 290
| caption3 = Previously established successive-approximation ADC example setup where an input voltage of 9.4V is provided, is illustrated in the figure.
}}
===Variants===
| |||