C-element: Difference between revisions

Revision as of 11:22, 30 November 2023

Revision as of 11:24, 30 November 2023

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[[Image:Delay assumptions.png|thumb|upright=1.5|Delays in the naive (based on [[Earle latch]]) implementation and environment]]

[[Image:Timing diagram of inclusive OR.png|thumb|upright=1.5|Timing diagram of a C-element and inclusive OR gate]]

[[Image:Join_element_stg.png|thumb|upright=1.5|Behavior of the environment with multiple input transitions <ref name="Kim71">I. Kimura, "[https://www.sciencedirect.com/science/article/pii/S0022000071800314?via%3Dihub Extensions of asynchronous circuits and the delay problem. Part II: Spike-free extensions and the delay problem of the second kind]," Journal of Computer and System Sciences, vol. 5, no. 2, pp. 129-162, 1971.</ref> (garbage branches <ref>A. Kushnerov and S. Bystrov, "[https://www.researchgate.net/profile/Alexander-Kushnerov/publication/371584542_Signal_Transition_Graphs_for_Asynchronous_Data_Path_Circuits/links/64918e63c41fb852dd1a1021/Signal-Transition-Graphs-for-Asynchronous-Data-Path-Circuits.pdf Signal transition graphs for asynchronous data path circuits]," Modeling and Analysis of Information Systems, vol. 30, no. 2, pp. 170-186, 2023.</ref>) (1)admissible (PDF)for SignalC-element Transitionand Graphsinadmissible for AsynchronousJoin Data Path Circuits. Available from: https://www.researchgate.net/publication/371584542_Signal_Transition_Graphs_for_Asynchronous_Data_Path_Circuits [accessed Nov 30 2023element]].

admissible for C-element and inadmissible for Join element]]

[[Image:Realizations_of_C_element.png|thumb|upright=1.8|Majority-gate realization of C-element and inclusive OR gate (a); Realizations proposed by Maevsky (b), Tsirlin (c) and Murphy (d)]]

[[Image:Single_gate_C_elements.png|thumb|upright=2.2|Static implementations of two- and three-input C-element<ref>I. E. Sutherland, [http://f-cpu.seul.org/new/micropipelines.pdf "Micropipelines]", Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989.</ref><ref>C. H. van Berkel, [http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=380B231B55BB4F45F6E4B72D4D273D44?doi=10.1.1.72.3108&rep=rep1&type=pdf "Beware the isochronic fork"], Report UR 003/91, Philips Research Laboratories, 1991.</ref>,<ref name="Mar10">V. B. Marakhovsky, [http://elib.spbstu.ru/dl/1945.pdf/download/1945.pdf Logic design of asynchronous circuits]. Slides on the course. CS&SE Department, SPbPU.</ref>]]