Priority encoder: Difference between revisions

Revision as of 10:11, 26 December 2023

Revision as of 17:11, 26 December 2023

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{{Short description|Priority encoder in Digital electronic circuit}}

A '''priority encoder''' is a [[Electronic circuit|circuit]] or [[algorithm]] that compresses multiple [[Binary code|binary]] inputs into a smaller number of outputs, similar to a [[Encoder (digital)|simple encoder]]. The output of a priority encoder is the binary representation of the [[Zero-based numbering|index]] of the [[Bit numbering|most significant]] activated line. In contrast to the simple encoder, if two or more inputs to the priority encoder are active at the same time, the input having the highest priority will take [[:wikt:precedence|precedence]]. It is an improvement on a simple encoder because it can handle all possible input combinations, but at the cost of extra logic.<ref>{{cite book |last1=Mano |first1=Moshe Morris |last2=Ciletti |first2=Michael D. |title=Digital Design |date=2007 |publisher=Pearson Prentice Hall |___location=Upper Saddle River, NJ |isbn=978-0-13-198924-5 |page=156 |edition=Fourth}}</ref>

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Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders – four 4-to-2 encoders having the signal source connected to their inputs, and the two remaining encoders take the output of the first four as input.

== Recursive construction of priority encoders<ref>{{Cite thesis|title=Architecture of block-RAM-based massively parallel memory structures : multi-ported memories and content-addressable memories|url=https://open.library.ubc.ca/cIRcle/collections/ubctheses/24/items/1.0314219|publisher=University of British Columbia|date=2016|first=Ameer M. S.|last=Abdelhadi}}</ref><ref>{{Cite book|last1=Abdelhadi|first1=Ameer M.S.|last2=Lemieux|first2=Guy G.F.|title=2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines |chapter=Modular SRAM-Based Binary Content-Addressable Memories |date=May 2015|pages=207–214|doi=10.1109/FCCM.2015.69|isbn=978-1-4799-9969-9|s2cid=16985129 }}</ref><ref>{{Cite book|last1=Abdelhadi|first1=Ameer M. S.|last2=Lemieux|first2=Guy G. F.|title=2014 International Conference on Field-Programmable Technology (FPT) |chapter=Deep and narrow binary content-addressable memories using FPGA-based BRAMs |date=December 2014|pages=318–321|doi=10.1109/FPT.2014.7082808|isbn=978-1-4799-6245-7|s2cid=2074456 }}</ref> ==