Cache hierarchy: Difference between revisions

Revision as of 16:50, 14 December 2023

Revision as of 06:43, 31 December 2023

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=== Inclusion policies ===

[[File:Inclusivecache.png|thumb|Inclusive cache organization|413x413px|alt=a memory system diagram showing a copy of the L1 within L2 and a copy of the L2 within L3.]]

Whether a block present in the upper cache layer can also be present in the lower cache level is governed by the memory system's [[Cache inclusion policy|inclusion policy]], which may be inclusive, exclusive or non-inclusive non-exclusive (NINE).<ref name=":0">{{Cite book|title=Fundamentals of Parallel Computer Architecture|last=Solihin|first=Yan|publisher=Solihin Publishing|year=2009|isbn=9780984163007|pages=Chapter 6: Introduction to Memory Hierarchy Organizationcn}}</ref>

With an inclusive policy, all the blocks present in the upper-level cache have to be present in the lower-level cache as well. Each upper-level cache component is a subset of the lower-level cache component. In this case, since there is a duplication of blocks, there is some wastage of memory. However, checking is faster.<ref name=":0" />{{cn}}

Under an exclusive policy, all the cache hierarchy components are completely exclusive, so that any element in the upper-level cache will not be present in any of the lower cache components. This enables complete usage of the cache memory. However, there is a high memory-access latency.<ref>{{Cite web|url=http://mercury.pr.erau.edu/~davisb22/papers/ispass04.pdf|title=Performance Evaluation of Exclusive Cache Hierarchies|access-date=2016-10-19|archive-date=2012-08-13|archive-url=https://web.archive.org/web/20120813003941/http://mercury.pr.erau.edu/~davisb22/papers/ispass04.pdf|url-status=dead}}</ref>

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=== Write policies ===

There are two policies which define the way in which a modified cache block will be updated in the main memory: write through and write back.<ref name=":0" />{{cn}}

In the case of write through policy, whenever the value of the cache block changes, it is further modified in the lower-level memory hierarchy as well.<ref>David A. Patterson; John L. Hennessy; 2017. Computer Organization and Design RISC-V Edition: The Hardware Software Interface. Elsevier Science. pp. 386–387. {{ISBN|978-0-12-812276-1}}.</ref> This policy ensures that the data is stored safely as it is written throughout the hierarchy.