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Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]] – a single piece of silicon that carries passive interconnect.<ref name="lawrence" /><ref>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{Webarchive|url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=2011-02-19 }}." November 1, 2010. Retrieved May 12, 2011.</ref> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a ''[[Heterogeneous computing|heterogeneous]] FPGA''.<ref>{{Cite web|url=https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-url=https://web.archive.org/web/20101105113516/http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-date=2010-11-05 |url-status=live|title=Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency|last=Saban|first=Kirk|date=December 11, 2012|website=xilinx.com|access-date=2018-11-30}}</ref>
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other die and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.<ref>{{cite web|url=http://www.intel.com/content/www/us/en/foundry/emib.html|title=Intel Custom Foundry EMIB|work=Intel|access-date=2015-07-13|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713230215/http://www.intel.com/content/www/us/en/foundry/emib.html|url-status=dead}}</ref
== Programming ==
{{See|Logic synthesis|Verification and validation|Place and route}}
To define the behavior of the FPGA, the user provides a design in a [[hardware description language]] (HDL) or as a [[schematic]] design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its
Using an [[electronic design automation]] tool, a technology-mapped [[netlist]] is generated. The netlist can then be fit to the actual FPGA architecture using a process called ''[[
The most common HDLs are [[VHDL]] and [[Verilog]] as well as extensions such as [[SystemVerilog]]. However, in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of [[assembly language]]s, there are moves{{by whom|date=July 2015}} to raise the [[abstraction level]] through the introduction of [[Hardware description language#HDL and programming languages|alternative languages]]. [[National Instruments]]' [[LabVIEW]] graphical programming language (sometimes referred to as ''G'') has an FPGA add-in module available to target and program FPGA hardware. [[Verilog]] was created to simplify the process making HDL more robust and flexible. Verilog is currently the most popular. Verilog creates a level of abstraction to hide away the details of its implementation. Verilog has a C-like syntax, unlike VHDL.<ref>{{Cite web|title=Battle Over the FPGA: VHDL vs Verilog! Who is the True Champ?|url=https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|access-date=2020-12-16|website=digilentinc.com|language=en-US|archive-date=2020-12-26|archive-url=https://web.archive.org/web/20201226074106/https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|url-status=dead}}</ref>
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