Field-programmable gate array: Difference between revisions

Revision as of 16:19, 11 February 2024

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As FPGA designs employ very fast I/O rates and bidirectional data [[Bus (computing)|buses]], it becomes a challenge to verify correct timing of valid data within setup time and hold time.<ref>{{cite book |last1=Oklobdzija |first1=Vojin G. |title=Digital Design and Fabrication |date=2017 |publisher=CRC Press |isbn=9780849386046 |url=https://books.google.com/books?id=VOnyWUUUj04C&dq=fpga+logic+gates+ram+blocks&pg=SA9-PA6}}</ref> [[Floorplan (microelectronics)|Floor planning]] helps resource allocation within FPGAs to meet these timing constraints.

Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable [[slew rate]] on each output pin, allowing the engineer to set low rates on lightly loaded pins that would otherwise [[Electrical resonance|ring]] or [[Coupling (electronics)|couple]] unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.<ref>{{cite web|url=http://wiki.altium.com/display/ADOH/FPGA+SI+Tutorial+-+Simulating+the+Reflection+Characteristics|title=FPGA Signal Integrity tutorial|work=altium.com|access-date=2010-06-15|archive-url=https://web.archive.org/web/20160307162907/http://wiki.altium.com/display/adoh/fpga+si+tutorial+-+simulating+the+reflection+characteristics|archive-date=2016-03-07|url-status=dead}}</ref><ref>[http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm NASA: FPGA drive strength] {{webarchive |url=https://web.archive.org/web/20101205230408/http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm |date=2010-12-05}}</ref> Also common are quartz-[[crystal oscillator]] driver circuitry, on-chip [[RC oscillator|resistance-capacitance oscillatorsoscillator]]s, and [[phase-locked loop]]s with embedded [[voltage-controlled oscillator]]s used for clock generation and management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential [[comparator]]s on input pins designed to be connected to [[differential signaling]] channels. A few [[mixed-signal integrated circuit|mixed signal]] FPGAs have integrated peripheral [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs) with analog signal conditioning blocks allowing them to operate as a [[System on a chip|system-on-a-chip]] (SoC).<ref>{{cite magazine |author=Mike Thompson |url=https://www.design-reuse.com/articles/16197/mixed-signal-fpgas-provide-green-power.html |title=Mixed-signal FPGAs provide GREEN POWER |magazine=Design & Reuse |date=2007-07-02}}</ref> Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and [[field-programmable analog array]] (FPAA), which carries analog values on its internal programmable interconnect fabric.

=== Logic blocks ===