Field-programmable gate array: Difference between revisions

Revision as of 16:24, 11 February 2024

Revision as of 16:25, 11 February 2024

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[[File:FPGA cell example.png|thumb|Simplified example illustration of a logic cell (LUT – [[Lookup table]], FA – [[Full adder]], DFF – [[D flip-flop|D-type flip-flop]])]]

The most common FPGA architecture consists of an array of [[logic block]]s called configurable logic blocks (CLBs), or logic array blocks (LABs), (depending on vendor), [[I/O address|I/O pads]], and routing channels.<ref name="FPGA" /> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and I/Os can be [[Routing (electronic design automation)|routed]]. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs."<ref>{{Cite journal |last1=M.b |first1=Swami |last2=V.p |first2=Pawar |date=2014-07-31 |title=VLSI DESIGN: A NEW APPROACH |url=https://bioinfopublication.org/pages/article.php?id=BIA0002301 |journal=Journal of Intelligence Systems |language=En |volume=4 |issue=1 |pages=60–63 |issn=2229-7057}}</ref>