Content deleted Content added
m →Integration: incorporate ... to => incorporate ... in |
m →3D architectures: pl. |
||
Line 95:
Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]] – a single piece of silicon that carries passive interconnect.<ref name="lawrence" /><ref>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{Webarchive|url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=2011-02-19 }}." November 1, 2010. Retrieved May 12, 2011.</ref> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a ''[[Heterogeneous computing|heterogeneous]] FPGA''.<ref>{{Cite web|url=https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-url=https://web.archive.org/web/20101105113516/http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-date=2010-11-05 |url-status=live|title=Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency|last=Saban|first=Kirk|date=December 11, 2012|website=xilinx.com|access-date=2018-11-30}}</ref>
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other
== Programming ==
| |||