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→Operation: add historical names |
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! Short<br/>Name !! Long<br/>Name !! Description
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| {{center|{{Overline|CS}}}} || {{center|Chip Select}} || [[Chip select]] signal ([[Logic level#Active state|active-low]]) from main (master).
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| {{center|SCLK}} || {{center|Serial Clock}} || [[Clock signal]] from main (master).
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| {{center|MOSI}} || {{center|Main Out, Sub In<br/>(Master Out, Slave In)}} || [[Serial communication|Serial data]] from main (master), highest bit first.
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| {{center|MISO}} || {{center|Main In, Sub Out<br/>(Master In, Slave Out)}} || [[Serial communication|Serial data]] from sub (slave), highest bit first.
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