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! Short<br/>Name !! Long<br/>Name !! Description<br/>(historical terms in parens)
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| {{center|{{Overline|CS}}}} || {{center|Chip Select}} || [[Logic level#Active state|Active-low]] [[Chip select|chip select signal]] from main (master) to enable a specific sub (slave).
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| {{center|SCLK}} || {{center|Serial Clock}} || [[Clock signal]] from main (master).
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