Non-volatile random-access memory: Difference between revisions

Revision as of 10:18, 15 January 2024

Revision as of 17:32, 13 February 2024

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Custom [[Read-only memory|ROM]] integrated circuits were one solution. The memory contents were stored as a pattern of the last mask used for manufacturing the integrated circuit, and so could not be modified once completed.

[[Programmable read-only memory|PROM]] improved on this design, allowing the chip to be written electrically by the end-user. PROM consists of a series of diodes that are initially all set to a single value, "1" for instance. By applying higher power than normal, a selected diode can be "''burned out"'' (like a [[Fuse (electrical)|fuse]]), thereby permanently setting that bit to "0". PROM facilitated prototyping and small -volume manufacturing. Many semiconductor manufacturers provided a PROM version of their mask ROM part, so that development [[firmware]] could be tested before ordering a mask ROM.

Currently, the best-known form of both NV-RAM and [[EEPROM]] memory is [[flash memory]]. Some drawbacks to flash memory include the requirement to write it in larger blocks than many computers can automatically address, and the relatively limited longevity of flash memory due to its finite number of write-erase cycles (as of January 2010 most consumer flash products can withstand only around 100,000 rewrites before memory begins to deteriorate){{Citation needed|date=January 2020}}. Another drawback is the performance limitations preventing flash from matching the response times and, in some cases, the random addressability offered by traditional forms of RAM. Several newer technologies are attempting to replace flash in certain roles, and some even claim to be a truly [[universal memory]], offering the performance of the best SRAM devices with the non-volatility of flash. As of June 2018 these alternatives have not yet become mainstream.

Those who required real RAM-like performance and non-volatility typically have had to use conventional RAM devices and a battery backup. For example, IBM PC's and successors beginning with the [[IBM PC AT]] used [[nonvolatile BIOS memory]], often called ''CMOS RAM'' or ''parameter RAM'', and this was a common solution in other early microcomputer systems like the original [[Apple Macintosh]], which used a small amount of memory powered by a battery for storing basic setup information like the selected boot volume. (The original IBM PC and PC XT instead used DIP switches to represent up to 24 bits of system configuration data; DIP or similar switches are another, primitive type of programmable ROM device that was widely used in the 1970s and 1980s for very small amounts of data—typically no more than 8 bytes.) Before industry standardization on the IBM PC architecture, some other microcomputer models used battery-backed RAM more extensively: for example, in the [[TRS-80 Model 100]]/Tandy 102, all of the main memory (8 KB minimum, 32 KB maximum) is battery-backed SRAM. Also, in the 1990s many video game software cartridges (e.g. for consoles such as the [[Sega Genesis]]) included battery-backed RAM to retain saved games, high scores, and similar data. Also, some arcade video game cabinets contain CPU modules that include battery-backed RAM containing keys for on-the-fly game software decryption. Much larger battery -backed memories are still used today as [[cache (computing)|caches]] for high-speed [[database]]s that require a performance level newer NVRAM devices have not yet managed to meet.

==Floating-gate MOSFET==<!-- linked here by redirect [[NOVRAM]] -->

A huge advance in NVRAM technology was the introduction of the [[floating-gate MOSFET]] transistor, which led to the introduction of ''erasable programmable read-only memory'', or [[EPROM]]. EPROM consists of a grid of transistors whose ''gate'' terminal (the "switch") is protected by a high-quality insulator. By "pushing" electrons onto the base with the application of higher-than-normal voltage, the electrons become trapped on the far side of the insulator, thereby permanently switching the transistor "on" ("1"). EPROM can be re-setreset to the "''base state"'' (all "1"s1s or "0"s0s, depending on the design) by applying [[ultraviolet]] light (UV). The UV [[photon]]s have enough energy to push the electrons through the insulator and return the base to a ground state. At that point the EPROM can be re-written from scratch.

An improvement on EPROM, [[EEPROM]], soon followed. The extra "E" stands for ''electrically'', referring to the ability to reset EEPROM using electricity instead of UV, making the devices much easier to use in practice. The bits are re-set with the application of even higher power through the other terminals of the transistor (''source'' and ''drain''). This high -power pulse, in effect, sucks the electrons through the insulator, returning it to the ground state. This process has the disadvantage of mechanically degrading the chip, however, so memory systems based on floating-gate transistors in general have short write-lifetimes, on the order of 10⁵ writes to any particular bit.

One approach to overcoming the rewrite count limitation is to have a standard [[Shadow Random Access Memory|SRAM]] where each bit is backed up by an EEPROM bit. In normal operation the chip functions as a fast SRAM and in case of power failure the content is quickly transferred to the EEPROM part, from where it gets loaded back at the next power up. Such chips were called '''NOVRAM'''s<!-- linked here by redirect [[NOVRAM]] --><ref>{{cite web|url=http://www.intersil.com/data/an/AN1146.pdf|title=X4C105 NOVRAM Features and Applications|first=Peter|last=Chan|date=2005-04-21|website=Intersil|archive-url=https://web.archive.org/web/20070614111904/http://www.intersil.com/data/an/AN1146.pdf|archive-date=2007-06-14}}</ref> by their manufacturers.

The basis of [[flash memory]] is identical to EEPROM, and differs largely in internal layout. Flash allows its memory to be written only in blocks, which greatly simplifies the internal wiring and allows for higher densities. [[Memory storage density]] is the main determinant of cost in most computer memory systems, and due to this flash has evolved into one of the lowest -cost solid-state memory devices available. Starting around 2000, demand for ever-greater quantities of flash have driven manufacturers to use only the latest fabrication systems in order to increase density as much as possible. Although fabrication limits are starting to come into play, new [[Multi-level cell|"multi-bit" techniques]] appear to be able to double or quadruple the density even at existing linewidthsline widths.

==Commercialized Alternatives==

Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like role. In addition, the high power needed to write the cells is a problem in low-power roles, where NVRAM is often used. The power also needs time to be "''built up"'' in a device known as a [[charge pump]], which makes writing dramatically slower than reading, often as much as 1,000 times. A number of new memory devices have been proposed to address these shortcomings.

===Ferroelectric RAM===

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===Phase-change RAM===

Another solid-state technology to see more than purely experimental development is [[Phase-change RAM]], or PRAM. PRAM is based on the same storage mechanism as writable [[CDs]] and [[DVD]]s, but reads them based on their changes in electrical resistance rather than changes in their optical properties. Considered a "dark horse" for some time, in 2006 [[Samsung]] announced the availability of a 512 Mbit part, considerably higher capacity than either MRAM or FeRAM. The areal density of these parts appears to be even higher than modern flash devices, the lower overall storage being due to the lack of multi-bit encoding. This announcement was followed by one from [[Intel]] and [[STMicroelectronics]], who demonstrated their own PRAM devices at the 2006 [[Intel Developer Forum]] in October.

[[Intel]] and [[Micron Technology]] had a joint venture to sell PRAM devices under the names [[3D XPoint]], Optane and QuantX, which was discontinued in July 2022.<ref>{{cite news |last1=Mann |first1=Tobias |title=Why Intel killed its Optane memory business |url=https://www.theregister.com/2022/07/29/intel_optane_memory_dead/ |access-date=2022-11-18 |work=The Register |publisher=Situation Publishing |date=2022-07-29}}</ref><ref>{{cite web |url=https://pcper.com/2017/06/how-3d-xpoint-phase-change-memory-works/ | title=HOW 3D XPOINT PHASE-CHANGE MEMORY WORKS | date=June 2, 2017 |author=Allyn Malventano | website=PC Perspective}}</ref>