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The 5-level paging is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, or the 5-level paging feature is not supported, the processor uses the 4-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}22}} This is similar to [[Physical Address Extension]] (PAE), where the third level of paging tables was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref>{{Cite web|url=https://learn.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=[[Microsoft Learn]]|date=June 2017 |language=en-us|access-date=2024-01-27}}</ref><ref name="x86-software-developers-manual" />{{Rp|page=4{{hyp}}14}}
Future processors may allow full 64-bit virtual address space by extending the size of page table descriptors to 12 bits (4096 page table entries) and memory offset to 16 bits (64 KiB page size) in the 4-level paging scheme or 21 bits (2 MiB page size) in the 5-level scheme.<Ref name=VA64/> Extending page table entry size from 64 to 128 bits would allow arbitrary page sizes, as additional hardware flags would change the size and operation of descriptors on lower paging levels.<Ref name=VA64/>
== Implementation ==
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