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Future processors may allow full 64-bit virtual address space by extending the size of page table descriptors to 12 bits (4096 page table entries) and memory offset to 16 bits (64 KiB page size) in the 4-level paging scheme or 21 bits (2 MiB page size) in the 5-level scheme.<Ref name=VA64/> Extending page table entry size from 64 to 128 bits would allow arbitrary page sizes, as additional hardware flags would change the size and operation of descriptors on lower paging levels.<Ref name=VA64/>
== Drawbacks ==▼
Adding another level of indirection makes [[page table]] "walks" longer.<ref>{{Cite conference|title=CSALT: Context Switch Aware Large TLB|book-title=MICRO-50: the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings |___location=Cambridge, MA|publisher=Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming|doi=10.1145/3123939.3124549|page=450|isbn=978-1-4503-4952-9|oclc=1032337814|date = 14 October 2017}}</ref> A page table walk occurs when either the processor's [[memory management unit]] or the memory management code in the operating system navigates the tree of page tables to find the [[page table entry]] corresponding to a virtual address.<ref>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/I1026235.html|title=ARM Information Center|website=infocenter.arm.com|access-date=2018-04-26}}</ref><ref name="x86-software-developers-manual">{{Cite book|url=https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html|title=Intel® 64 and IA-32 Architectures Software Developer's Manual|volume=3A|publisher=[[Intel Corporation]]}}</ref>{{Rp|page=4{{hyp}}22}} This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.<ref name="cse-451-paging-tlbs-slides" /> In practice this cost is greatly mitigated by caches such as the [[translation lookaside buffer]] (TLB).<ref name="cse-451-paging-tlbs-slides">{{Cite web|url=https://courses.cs.washington.edu/courses/cse451/08au/lectures/10-paging_TLBs.pdf|title=CSE 451: Operating Systems: Paging & TLBs|last=Levy|first=Hank|author-link=Hank Levy (computer scientist)|date=Autumn 2008|website=[[University of Washington]]|access-date=26 April 2018}}</ref> Future extensions may reduce page walks by limiting virtual address space per application, with dedicated hardware flags in an extended 128 bit page table entry, and allowing a larger 64 KiB or 2 MiB [[Page (computer memory)|page size]]s and backward compatibility with 4 KB page operations.<Ref name=VA64>{{cite patent | country = US | number = 9858198 | status = patent | title = 64KB page system that supports 4KB page operation | pridate = 2015-06-26 | fdate = 2015-06-26 | pubdate = 2016-12-29 | gdate = 2018-01-02 | invent1 = Larry Seiler | assign1 = Intel Corp.}} </ref>▼
== Implementation ==
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Support for the extension was submitted as a set of patches to the [[Linux kernel]] on 8 December 2016.<ref name="phoronix">{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=Intel-5-Level-Paging|title=Intel Working On 5-Level Paging To Increase Linux Virtual/Physical Address Space - Phoronix|author=Michael Larabel|date=9 December 2016|website=[[Phoronix]]|language=en|access-date=2018-04-26}}</ref> As was reported on the [[Linux kernel mailing list]], it consisted of extending the Linux memory model to use five levels rather than four.<ref>{{Cite mailing list|url=http://lkml.iu.edu/hypermail/linux/kernel/1612.1/00383.html|title=[RFC, PATCHv1 00/28] 5-level paging|last=Shutemov|first=Kirill A.|mailing-list=[[Linux kernel mailing list]]|date=December 8, 2016|access-date=2018-04-26}}</ref> This is because, although Linux [[Abstraction (software engineering)|abstracts]] the details of the page tables, it still depends on having a number of levels in its own representation. When an [[Instruction set architecture|architecture]] supports fewer levels, Linux emulates extra levels that do nothing.<ref>{{Cite web|url=https://www.kernel.org/doc/gorman/html/understand/understand006.html|title=Page Table Management|website=www.kernel.org|access-date=2018-04-26}}</ref> A similar change was previously made to extend from three levels to four.<ref>{{Cite web|url=https://lwn.net/Articles/106177/|title=Four-level page tables [LWN.net]|date=October 12, 2004|website=lwn.net|access-date=2018-04-26}}</ref>
▲== Drawbacks ==
▲Adding another level of indirection makes [[page table]] "walks" longer.<ref>{{Cite conference|title=CSALT: Context Switch Aware Large TLB|book-title=MICRO-50: the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings |___location=Cambridge, MA|publisher=Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming|doi=10.1145/3123939.3124549|page=450|isbn=978-1-4503-4952-9|oclc=1032337814|date = 14 October 2017}}</ref> A page table walk occurs when either the processor's [[memory management unit]] or the memory management code in the operating system navigates the tree of page tables to find the [[page table entry]] corresponding to a virtual address.<ref>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/I1026235.html|title=ARM Information Center|website=infocenter.arm.com|access-date=2018-04-26}}</ref><ref name="x86-software-developers-manual">{{Cite book|url=https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html|title=Intel® 64 and IA-32 Architectures Software Developer's Manual|volume=3A|publisher=[[Intel Corporation]]}}</ref>{{Rp|page=4{{hyp}}22}} This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.<ref name="cse-451-paging-tlbs-slides" /> In practice this cost is greatly mitigated by caches such as the [[translation lookaside buffer]] (TLB).<ref name="cse-451-paging-tlbs-slides">{{Cite web|url=https://courses.cs.washington.edu/courses/cse451/08au/lectures/10-paging_TLBs.pdf|title=CSE 451: Operating Systems: Paging & TLBs|last=Levy|first=Hank|author-link=Hank Levy (computer scientist)|date=Autumn 2008|website=[[University of Washington]]|access-date=26 April 2018}}</ref> Future extensions may reduce page walks by limiting virtual address space per application, with dedicated hardware flags in an extended 128 bit page table entry, and allowing a larger 64 KiB or 2 MiB [[Page (computer memory)|page size]]s and backward compatibility with 4 KB page operations.<Ref name=VA64>{{cite patent | country = US | number = 9858198 | status = patent | title = 64KB page system that supports 4KB page operation | pridate = 2015-06-26 | fdate = 2015-06-26 | pubdate = 2016-12-29 | gdate = 2018-01-02 | invent1 = Larry Seiler | assign1 = Intel Corp.}} </ref>
== References ==
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