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====Hardware Costs====
The additional hardware cost of this type of multithreading is that ''each'' pipeline stage now has to maintain ''multiple'' register sets, one set for each executing thread. For example, for a processor with a 7-stage pipeline that can issue 3 instructions per cycle, the register hardware needs to be replicated 21 times. Again, shared resources such as caches and TLBs have to be sized for the large number of active threads.
====Examples====
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