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Hardware techniques used to support [[thread (computer science)|multithreading]] often parallel the software techniques used
for [[computer multitasking]] of computer programs.
For this type of multithreading, a major area of research is the thread scheduler which must quickly choose among▼
the list of ready-to-run threads to execute next as well as maintain the read-to-run and stalled thread lists. ▼
An important topic are the different thread priority schemes that can be used by the scheduler. ▼
The thread scheduler might be implemented totally in software or totally in hardware or as a hw/sw combination.▼
Another area of research is what type of events should cause a thread switch - cache misses, inter-thread communication, ▼
[[Direct memory access|DMA]] completion, etc. ▼
===Block Multi-threading===
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register set. For example, to quickly switch between two threads, the register hardware needs to be instantiated twice.
▲====Research Topics====
▲For this type of multithreading, a major area of research is the thread scheduler which must quickly choose among
▲the list of ready-to-run threads to execute next as well as maintain the read-to-run and stalled thread lists.
▲An important topic are the different thread priority schemes that can be used by the scheduler.
▲The thread scheduler might be implemented totally in software or totally in hardware or as a hw/sw combination.
▲Another area of research is what type of events should cause a thread switch - cache misses, inter-thread communication,
▲[[Direct memory access|DMA]] completion, etc.
====Examples====
* [[MIPS architecture]] Multi-Threaded ASE▼
===Interleaved Multi-threading===
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* [[Sun Microsystem]] [[Ultrasparc T1]]
* [[Lexra]] NetVortex
▲* [[MIPS architecture]] Multi-Threaded ASE
* [[Raza Microelectronics Inc]] XLR
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