Memory controller: Difference between revisions

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A '''memory controller''', isalso aknown digitalas circuit that manages the flow of data going to and from a computer's [[main ''memory]]. A memorychip controller can be a separate chip or integrated into another chip, such as being placed on the same [[die''' (integrated circuit'''MCC''')|die]] or as an integral part of a [[microprocessor]]; in the latter case, it is usually called an '''integrated memory controller unit''' ('''IMCMCU''')., is Aa memorydigital controllercircuit isthat sometimesmanages alsothe calledflow of data going to and from a computer'''memorys chip[[main controller''' ('''MCC''')memory]].<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref> or a '''memory controller unit''' ('''MCU''').<ref>{{cite book |last1=Neat |first1=Adam G. |url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100 |title=Maximizing Performance and Scalability with IBM WebSphere |access-date=62003-12-04 February 2015|isbn=9781590591307|last1=Neat|first1=Adam G.|access-date=2003-12-046 February 2015}}</ref> When a memory controller is integrated into another chip, such as being placed on the same [[die (integrated circuit)|die]] or as an integral part of a [[microprocessor]], it is usually called an '''integrated memory controller''' ('''IMC''').

Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to [[Memory refresh|refresh]] the DRAM in order to prevent losing data written to it, as otherwise the [[capacitors]] leak their [[electric charge|charge]] within not more than 64 milliseconds. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.

Memory controllers contain the logic necessary to read and write to DRAM, and to "refresh" the DRAM. Without periodic refresh, DRAM will lose the data written to it. Some memory controllers include [[error detection and correction]] hardware.

Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> A common form of memory controller is the [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]].

== History ==

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Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM [[POWER8]], which uses external [[Centaur (computing)|Centaur]] chips that are mounted onto [[DIMM]] modules and act as memory buffers, [[L4 cache]] chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<ref>{{cite web|url=https://www.itjungle.com/2016/10/17/tfh101716-story02/|title=IBM Brings DDR4 Memory To Bear On Power Systems|last=Prickett Morgan|first=Timothy|date=2016-10-17|website=IT Jungle|pages=1|access-date=2017-09-07}}</ref>

== Purpose ==

Memory controllers contain the logic necessary to read and write to [[dynamic random access memory|DRAM]], and to [[memory refresh|"refresh" the DRAM]]. Without constant refreshes, DRAM will lose the data written to it as the [[capacitors]] leak their [[electric charge|charge]] within a fraction of a second (not more than 64 milliseconds according to [[JEDEC]] standards).

Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation.

Bus width is the number of parallel lines available to communicate with the memory cell. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems and video cards (typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a [[128-bit]] memory device).

Some memory controllers, such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref>

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