Content deleted Content added
→Recent implementation models: chronology arrange Tags: Mobile edit Mobile web edit |
+link |
||
Line 2:
'''Cache hierarchy,''' or '''multi-level cache''', is a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly requested data is cached in high-speed access memory stores, allowing swifter access by [[central processing unit]] (CPU) cores.
Cache hierarchy is a form and part of [[memory hierarchy]] and can be considered a form of [[tiered storage]].<ref name="CA:QA">{{cite book |last1=Hennessy |first1=John L |last2=Patterson |first2=David A |last3=Asanović |first3=Krste |author3-link=Krste Asanović |last4=Bakos |first4=Jason D |last5=Colwell |first5=Robert P |last6=Bhattacharjee |first6=Abhishek |last7=Conte |first7=Thomas M |last8=Duato |first8=José |last9=Franklin |first9=Diana |last10=Goldberg |first10=David |last11=Jouppi |first11=Norman P |last12=Li |first12=Sheng |last13=Muralimanohar |first13=Naveen |last14=Peterson |first14=Gregory D |last15=Pinkston |first15=Timothy Mark |last16=Ranganathan |first16=Prakash |last17=Wood |first17=David Allen |last18=Young |first18=Clifford |last19=Zaky |first19=Amr |title=Computer Architecture: a Quantitative Approach |date=2011 |isbn=978-0128119051 |edition= Sixth |language=en|oclc=983459758 }}</ref> This design was intended to allow CPU cores to process faster despite the [[CAS latency|memory latency]] of [[computer data storage|main memory]] access. Accessing main memory can act as a bottleneck for [[computer performance|CPU core performance]] as the CPU waits for data, while making all of main memory high-speed may be prohibitively expensive. High-speed caches are a compromise allowing high-speed access to the data most-used by the CPU, permitting a faster [[clock rate|CPU clock]].<ref>{{Cite web|url=http://gec.di.uminho.pt/discip/minf/ac0102/0945CacheLevel.pdf|title=Cache: Why Level It}}</ref>
[[File:Cache Organization.png|thumb|right|429x429px|Generic multi-level cache organization|alt=Process architecture diagram showing four independent processors each linked through cache systems to main memory and input-output system.]]
| |||