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<ref name="Lin">{{cite journal |author-first1=C.-H. |author-last1=Lin |display-authors=et al |title=Hierarchical Value Cache Encoding for Off-Chip Data Bus |journal=ISLPED |date=2006}}</ref>
<ref name="Sector">{{cite web |url=http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf |title=Transition Reduction in Memory Buses Using Sector-based Encoding Techniques |author-first1=Yazdan |author-last1=Aghaghiri |author-first2=Farzan |author-last2=Fallah |author-first3=Massoud |author-last3=Pedram}}</ref>
<ref name="Deogun">{{cite journal |author-first1=H. |author-last1=Deogun |author-first2=R. |author-last2=Rao |author-first3=D. |author-last3=Sylvester |author-first4=D. |author-last4=Blaauw |author-link4=D. Blaauw |title=Leakage- and crosstalk-aware bus encoding for total power reduction |journal=Proceedings of the 41st Design Automation Conference |pages=779–782 |date=June 2004}}</ref>
<ref name="Khan">{{cite journal |author-first1=Z. |author-last1=Khan |author-first2=T. |author-last2=Arslan |author-first3=A. |author-last3=Erdogan |title=A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems |journal=Proceedings of the 18th International Conference on VLSI Design |pages=751–756 |date=January 2005}}</ref>
<ref name="VLSI">{{cite journal |url=http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf |title=Power Optimization of Core-Based Systems by Address Bus Encoding |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=Massimo |author-last4=Poncino |author-first5=Stefano |author-last5=Quer |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=6 |number=4 |date=December 1998}}</ref>
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