Digital signal processor: Difference between revisions

Revision as of 19:50, 8 February 2024

Revision as of 16:53, 25 April 2024

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{{Short description|Specialized microprocessor optimized for digital signal processing}}

[[File:Digital Signal Processor 9997.jpg|thumb|An L7A1045 DSP chip, as used in several [[Sampler (musical instrument)#Akai|Akai samplers]] and the [[Hyper Neo Geo 64]] arcade board]]

[[File:NeXTcube motherboard.jpg|thumb|The [[NeXTcube]] from 1990 had a [[Motorola 68040]] (25  MHz) and a digital signal processor [[Motorola 56001]] with 25  MHz which was directly accessible via an interface.]]

A '''digital signal processor''' ('''DSP''') is a specialized [[microprocessor]] chip, with its architecture optimized for the operational needs of [[digital signal processing]].<ref>{{cite book |editor-last1=Yovits |editor-first1=Marshall C. |last1=Dyer |first1=Stephen A. |last2=Harms |first2=Brian K. |chapter=Digital Signal Processing |title=Advances in Computers |date=1993-08-13 |volume=37 |pages=59{{hyphen}}118 |publisher=[[Academic Press]] |doi=10.1016/S0065-2458(08)60403-9 |isbn=978-0120121373 |issn=0065-2458 |lccn=59015761 |chapter-url=https://books.google.com/books?id=vL-bB7GALAwC&pg=PA104 |ol=OL10070096M |oclc=858439915 |df=dmy-all}}</ref>{{rp|pages=104{{hyphen}}107}}<ref name="Liptak">{{cite book |last=Liptak |first=B. G. |title=Process Control and Optimization |series=Instrument Engineers' Handbook |edition=4th |year=2006 |volume=2 |pages=11–12 |publisher=CRC Press |isbn=978-0849310812 |url=https://books.google.com/books?id=TxKynbyaIAMC&pg=PA11 |via=[[Google Books]]}}</ref> DSPs are [[semiconductor device fabrication|fabricated]] on [[MOSFET|metal–oxide–semiconductor]] (MOS) [[integrated circuit]] chips.<ref name="computerhistory1979">{{cite web |title=1979: Single Chip Digital Signal Processor Introduced |url=https://www.computerhistory.org/siliconengine/single-chip-digital-signal-processor-introduced/ |access-date=14 October 2019 |website=The Silicon Engine |publisher=[[Computer History Museum]]}}</ref><ref name="edn">{{cite web |last1=Taranovich |first1=Steve |date=August 27, 2012 |title=30 years of DSP: From a child's toy to 4G and beyond |url=https://www.edn.com/design/systems-design/4394792/30-years-of-DSP--From-a-child-s-toy-to-4G-and-beyond |access-date=14 October 2019 |website=[[EDN (magazine)|EDN]]}}</ref> They are widely used in [[audio signal processing]], [[telecommunications]], [[digital image processing]], [[radar]], [[sonar]] and [[speech recognition]] systems, and in common [[consumer electronic]] devices such as [[mobile phones]], [[disk drives]] and [[high-definition television]] (HDTV) products.<ref name="computerhistory1979"/>

The goal of a DSP is usually to measure, filter or compress continuous real-world [[analog signals]]. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as [[mobile phone]]s because of power consumption constraints.<ref name="schaum-2004">{{cite web

|url=http://ptolemy.eecs.berkeley.edu/~kienhuis/ftp/07g.pdf

|title=Architectures and Design techniques for energy efficient embedded DSP and multimedia processing

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[[Image:DSP block diagram.svg|thumb|410px|A typical digital processing system]]

Digital signal processing (DSP) [[algorithm]]s typically require a large number of mathematical operations to be performed quickly and repeatedly on a series of data samples. Signals (perhaps from audio or video sensors) are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints on [[latency (engineering)|latency]]; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.

Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power efficiency constraints.<ref name="schaum-2004"/> A specialized DSP, however, will tend to provide a lower-cost solution, with better performance, lower latency, and no requirements for specialised cooling or large batteries.{{citation needed|date=February 2013}}

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DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as the [[Harvard architecture]] or Modified [[von Neumann architecture]], which use separate program and data memories (sometimes even concurrent access on multiple data buses).

DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance{{clarify|date=November 2015}}. In addition, extensive use of [[Direct memory access|DMA]] is employed.

=====Addressing and virtual memory=====

DSPs frequently use multi-tasking operating systems, but have no support for [[virtual memory]] or memory protection. Operating systems that use virtual memory require more time for [[context switching]] among [[process (computing)|processes]], which increases latency.

*Hardware modulo addressing

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[[File:TRW 1010J 1.jpg|thumb|TRW TDC1010 multiplier-accumulator]]

===Development===

In 1976, Richard Wiggins proposed the [[Speak & Spell (toy)|Speak & Spell]] concept to Paul Breedlove, Larry Brantingham, and Gene Frantz at [[Texas Instruments]]' Dallas research facility. Two years later in 1978, they produced the first Speak & Spell, with the technological centerpiece being the [[TMS5100]],<ref>{{cite web |publisher=IEEE |work=IEEE Milestones |title=Speak & Spell, the First Use of a Digital Signal Processing IC for Speech Generation, 1978 |url=http://www.ieeeghn.org/wiki/index.php/Milestones:Speak_%26_Spell,_the_First_Use_of_a_Digital_Signal_Processing_IC_for_Speech_Generation,_1978 |access-date=2012-03-02}}</ref> the industry's first digital signal processor. It also set other milestones, being the first chip to use linear predictive coding to perform [[speech synthesis]].<ref>{{cite web |author=Bogdanowicz, A. |title=IEEE Milestones Honor Three |url=http://theinstitute.ieee.org/technology-focus/technology-history/ieee-milestones-honor-four476 |work=The Institute |publisher=IEEE |date=2009-10-06 |access-date=2012-03-02 |archive-url=https://web.archive.org/web/20160304200210/http://theinstitute.ieee.org/technology-focus/technology-history/ieee-milestones-honor-four476 |archive-date=2016-03-04 |url-status=dead}}</ref> The chip was made possible with a [[10 µm process|7 µm]] [[PMOS logic|PMOS]] [[semiconductor device fabrication|fabrication process]].<ref>{{cite book |last1=Khan |first1=Gul N. |last2=Iniewski |first2=Krzysztof |title=Embedded and Networking Systems: Design, Software, and Implementation |date=2017 |publisher=[[CRC Press]] |isbn=9781351831567 |page=2 |url=https://books.google.com/books?id=vx8uDwAAQBAJ&pg=PR14}}</ref>

In 1978, [[American Microsystems]] (AMI) released the S2811.<ref name="computerhistory1979"/><ref name="edn"/> The AMI S2811 "signal processing peripheral", like many later DSPs, has a hardware multiplier that enables it to do [[multiply–accumulate operation]] in a single instruction.<ref>Alberto Luis Andres. [http://scholarworks.csun.edu/bitstream/handle/10211.3/126902/AndresAlberto1983.pdf "Digital Graphic Audio Equalizer"]. p. 48.</ref> The S2281 was the first [[integrated circuit]] chip specifically designed as a DSP, and fabricated using vertical metal oxide semiconductor ([[VMOS]], V-groove MOS), a technology that had previously not been mass-produced.<ref name="edn"/> It was designed as a microprocessor peripheral, for the [[Motorola 6800]],<ref name="computerhistory1979"/> and it had to be initialized by the host. The S2811 was not successful in the market.

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Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, (E)[[Direct memory access|DMA]] circuitry, and a wider bus system. Not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300.

[[Texas Instruments]] produces the [[TMS320C6000|C6000]] series DSPs, which have clock speeds of 1.2&nbsp;GHz and implement separate instruction and data caches. They also have an 8 &nbsp;MiB 2nd level cache and 64 EDMA channels. The top models are capable of as many as 8000 MIPS ([[millions of instructions per second]]), use VLIW ([[very long instruction word]]), perform eight operations per clock-cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc). TMS320C6474 chips each have three such DSPs, and the newest generation C6000 chips support floating point as well as fixed point processing.

[[Freescale]] produces a multi-core DSP family, the MSC81xx. The MSC81xx is based on StarCore Architecture processors and the latest MSC8144 DSP combines four programmable SC3400 StarCore DSP cores. Each SC3400 StarCore DSP core has a clock speed of 1&nbsp;GHz.

[[XMOS]] produces a multi-core multi-threaded line of processor well suited to DSP operations, They come in various speeds ranging from 400 to 1600 MIPS. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. Threads communicate between each other with buffered channels that are capable of up to 80 &nbsp;Mbit/s. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs

[[CEVA, Inc.]] produces and licenses three distinct families of DSPs. Perhaps the best known and most widely deployed is the CEVA-TeakLite DSP family, a classic memory-based architecture, with 16-bit or 32-bit word-widths and single or dual [[Multiply–accumulate operation|MACs]]. The CEVA-X DSP family offers a combination of VLIW and SIMD architectures, with different members of the family offering dual or quad 16-bit MACs. The CEVA-XC DSP family targets [[Software-defined radio|Software-defined Radio (SDR)]] modem designs and leverages a unique combination of VLIW and Vector architectures with 32 16-bit MACs.