AVR microcontrollers: Difference between revisions

Revision as of 06:25, 30 March 2024

Revision as of 17:06, 25 April 2024

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{{Short description|Family of microcontrollers}}

{{About|the series of AVR microcontrollers|the AVR instruction set|Atmel AVR instruction set}}

[[File:Avr_logo.svg|right|thumb|AVR logo]]

[[File:AVR_group.jpg|right|thumb|Various older AVR microcontrollers: ATmega8 in 28-pin narrow dual in-line package ([[Dual in-line package|DIP]]-28N), ATxmega128A1 in 100-pin thin quad flat pack ([[TQFP]]-100) package, ATtiny45 in 8-pin small outline ([[Small Outline Integrated Circuit|SO]]-8) package.]]

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The ATtiny series features small package microcontrollers with a limited peripheral set available. However, the improved tinyAVR 0/1/2-series (released in 2016) include:

* Peripherals equal to or exceed megaAVR 0-series

* Event System

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The ATmega series features microcontrollers that provide an extended instruction set (multiply instructions and instructions for handling larger program memories), an extensive peripheral set, a solid amount of program memory, as well as a wide range of pins available. The megaAVR 0-series (released in 2016) also has functionality such as:

* Event system

* New peripherals with enhanced functionality

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* [[Processor register|Register]] locations R0 to R15 have more limited addressing capabilities than register locations R16 to R31.

* I/O ports 0 to 31 can be bit addressed, unlike I/O ports 32 to 63.

* CLR (clear all bits to zero) affects flags, while SER (set all bits to one) does not, even though they are complementary instructions. (CLR is pseudo-op for EOR R, R; while SER is short for LDI R,$FF. Arithmetic operations such as EOR modify flags, while moves/loads/stores/branches such as LDI do not.)

* Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory.

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* [[Controller area network|CAN]] controller support

* [[Universal Serial Bus|USB]] controller support

** Proper full-speed (12  Mbit/s) hardware & Hub controller with embedded AVR.

** Also freely available low-speed (1.5  Mbit/s) ([[Human interface device|HID]]) [[Bit-banging|bitbanging]] software emulations

* [[Ethernet]] controller support

* [[Liquid crystal display|LCD]] controller support

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=== STK200 starter kit ===

The STK200 starter kit and development system has a [[Dual in-line package|DIP]] socket that can host an AVR chip in a 40, 20, or 8-pin package. The board has a 4 MHz clock source, 8 [[light-emitting diode]] (LED)s, 8 input buttons, an [[RS-232]] port, a socket for a 32  KB [[Static random-access memory|SRAM]] and numerous general I/O. The chip can be programmed with a dongle connected to the parallel port.

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Target operating voltage ranges of 1.62V to 5.5V are supported as well as the following clock ranges:

* Supports JTAG & PDI clock frequencies from 32  kHz to 7.5  MHz

* Supports aWire baud rates from 7.5  kbit/s to 7  Mbit/s

* Supports debugWIRE baud rates from 4  kbit/s to 0.5  Mbit/s

* Supports SPI clock frequencies from 8  kHz to 5  MHz

* Supports SWD clock frequencies from 32  kHz to 2  MHz

The ICE is supported by the Microchip Studio IDE, as well as a command line interface (atprogram).

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* avr_core,<ref>{{cite web|url=http://opencores.org/project,avr_core|title=AVR Core :: Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[VHDL]], is a clone aimed at being as close as possible to the ATmega103.

* Navré,<ref>{{cite web|url=http://opencores.org/project,navre|title=Navré AVR clone (8-bit RISC) Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[Verilog]], implements all [[Atmel AVR instruction set|Classic Core]] instructions and is aimed at high performance and low resource usage. It does not support [[interrupt]]s.

* softavrcore,<ref>{{cite web|url=https://opencores.org/projects/softavrcore|title=Soft AVR Core + Interfaces Overview|publisher=OpenCores|access-date=2020-06-16}}</ref> written in [[Verilog]], implements the [[AVR instruction set]] up to AVR5, supports interrupts along with optional automatic interrupt acknowledgement, power saving via [[Idle (CPU)|sleep mode]] plus some peripheral interfaces and [[Hardware_acceleration|hardware accelerators]] (such as [[UART]], [[Serial_Peripheral_Interface|SPI]], [[cyclic redundancy check]] calculation unit and [[Programmable_interval_timer|system timers]]). These peripherals demonstrate how could these be attached to and configured for this core. Within the package, a full-featured [[FreeRTOS]] port is also available as an example for the core + peripheral utilization.

* The opencores project [http://opencores.org/project,cpu_lecture CPU lecture]<ref>{{cite web|url=http://opencores.org/project,cpu_lecture|title=CPU lecture|publisher=OpenCores|access-date=2015-02-16}}</ref> written in [[VHDL]] by Dr. Jürgen Sauermann explains in detail how to design a complete AVR-based [[system on a chip]] (SoC).