Memory controller: Difference between revisions

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Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to [[Memory refresh|refresh]] the DRAM in order to prevent losing data written to it, as otherwise the [[capacitors]] leak their [[electric charge|charge]] within not more than 64 milliseconds. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.

Some memory controllers, such as the one integrated into [[PowerQUICC|Power QUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> A common form of memory controller is the [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]].

== History ==