Gate array: Difference between revisions

Revision as of 03:01, 30 April 2024

Revision as of 04:18, 12 May 2024

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[[IBM]] developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally. [[Fairchild Semiconductor]] also flirted briefly in the late 1960s with bipolar arrays [[diode–transistor logic]] and transistor-transistor logic called Micromosaic and Polycell.<ref name=":0">{{Cite web|url=http://www.computerhistory.org/siliconengine/application-specific-integrated-circuits-employ-computer-aided-design/|title=1967: Application Specific Integrated Circuits employ Computer-Aided Design|work=The Silicon Engine|publisher=[[Computer History Museum]]|access-date=2018-01-28}}</ref>

[[CMOS]] (complementary [[metal–oxide–semiconductor]]) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp<ref name=":1">{{Cite book|url=http://www.computerhistory.org/collections/catalog/102706880|title=Lipp, Bob oral history|publisher=[[Computer History Museum]]|date=14 February 2017 |access-date=2018-01-28}}</ref><ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/people/|title=People|work=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref> in 1974 for International Microcircuits, Inc.<ref name=":0" /> (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed [[10 µmμm process|7.5 micron]] single-level metal CMOS technology and ranged from 50 to 400 [[metal gate|gates]]. [[Computer-aided design]] (CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.

This product pioneered several features that went on to become standard in future designs. The most important were: the strict organization of [[NMOS logic|n-channel]] and [[PMOS logic|p-channel transistors]] in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was somewhat tedious and error-prone due to the lack of good software tools.<ref name=":0" /> IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer. [[Rubylith]] sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage; drawings were still manual and then "hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.