Revision as of 10:48, 22 April 2024 edit MyIpIsLocalhost (talk \| contribs) 20 edits 8 channel max -> updated to 12 channel ← Previous edit		Revision as of 18:25, 15 May 2024 edit undo PantheraLeo1359531 (talk \| contribs) 398 edits →Dodeca-channel architecture Next edit →
Line 178: == Dodeca-channel architecture == [[File:AMD Epyc 9754 in Dual-CPU-Socket-Serversystem (极客湾Geekerwan) 07.png\|thumb\|Server system containing two AMD Epyc CPUs with one dodeca-channel per CPU]] Dodeca-channel or 12-channel memory architecture is introduced with AMD's server processors from their [[Epyc#Fourth generation Epyc (Genoa, Bergamo and Siena)\|Epyc 9004]] platform released in 2022, using [[DDR5]] memory.<ref>{{Cite web \|last=Goetting \|first=Chris \|date=2022-11-10 \|title=AMD 4th Gen EPYC 9004 Series Launched: Genoa Tested In A Data Center Benchmark Gauntlet \|url=https://hothardware.com/reviews/amd-genoa-data-center-cpu-launch \|access-date=2023-12-07 \|website=HotHardware \|language=en-us}}</ref>

Multi-channel memory architecture: Difference between revisions