Content deleted Content added
Reverted good faith edits by The Maelstorm 40K (talk): Sources at PowerQUICC have this as one word |
Citation bot (talk | contribs) Added publisher. | Use this bot. Report bugs. | Suggested by Dominic3203 | Category:Computer memory | #UCB_Category 139/196 |
||
Line 2:
{{Update|date=August 2022}}
A '''memory controller''', also known as '''memory chip controller''' ('''MCC''') or a '''memory controller unit''' ('''MCU'''), is a digital circuit that manages the flow of data going to and from a computer's [[main memory]].<ref>Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."</ref><ref>{{cite book |last1=Neat |first1=Adam G. |url=https://books.google.com/books?id=PJ49xcoRb1QC&q=%22memory+controller+unit%22&pg=PA100 |title=Maximizing Performance and Scalability with IBM WebSphere |date=2003-12-04 |publisher=Apress |isbn=9781590591307 |access-date=6 February 2015}}</ref> When a memory controller is integrated into another chip, such as being placed on the same [[die (integrated circuit)|die]] or as an integral part of a [[microprocessor]], it is usually called an '''integrated memory controller''' ('''IMC''').
Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to [[Memory refresh|refresh]] the DRAM in order to prevent losing data written to it, as otherwise the [[capacitors]] leak their [[electric charge|charge]] within not more than 64 milliseconds. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.
| |||