Revision as of 19:57, 8 May 2024 edit Frap (talk \| contribs) Extended confirmed users, File movers, Pending changes reviewers, Rollbackers 35,588 edits Fix page range. ← Previous edit		Revision as of 20:37, 28 May 2024 edit undo Xose.vazquez (talk \| contribs) Extended confirmed users 10,808 edits →Instruction sets: X86-64#Microarchitecture_levels Next edit →
Line 233: \| [[x86]] \| 16, 32, 64<br />(16→32→64) \| v4 (x86-64) \| \| 1978 \| 2 (integer)<br />3 ([[Advanced Vector Extensions\|AVX]]){{efn\|The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.}}<br />4 ([[FMA instruction set\|FMA4]] and <code>VPBLENDVPx</code>)<ref>{{cite web\|url=https://www.amd.com/system/files/TechDocs/43479.pdf\|title=AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions\|date=November 2009\|publisher=[[AMD]]}}</ref><br />

Comparison of instruction set architectures: Difference between revisions