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Verification methods for [[computer hardware|hardware]] design as well as early [[software]] and [[firmware]] co-design have become mainstream. Prototyping SoC and ASIC designs with one or more FPGAs and [[electronic design automation]] (EDA) software has become a good method to do this.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=July 17, 2018 |language=en-US|access-date=2018-10-17}}</ref>
==Importance==
#Running a SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on [[Electronic circuit simulation|software simulations]] to verify that their hardware design is sound. About a third of all current SoC designs are fault-free during first silicon pass, with nearly half of all re-spins caused by functional logic errors.<ref name ="soc">{{Cite web |url=http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |title=SOCcentral: Getting the Most Out of ASIC Prototyping with FPGAs (EE Times Programmable Logic Designline 30794) |access-date=October 9, 2012 |archive-url=https://archive.today/20130202104923/http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |archive-date=February 2, 2013 |url-status=dead }}</ref> A single prototyping platform can provide verification for hardware, firmware, and application software design functionality before the first silicon pass.<ref>{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|access-date=2018-10-07}}</ref>
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