Programmable ROM: Difference between revisions

Revision as of 17:16, 8 June 2024

Revision as of 17:12, 9 June 2024

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* [https://archive.org/details/bitsavers_inteldataBMay77_21293903 1977 Intel Memory Design Handbook] - archive.org

* [https://www.intel-vintage.info/intelmemory.htm Intel PROM datasheets] - intel-vintage.info

* View the US "Switch Matrix" Patent #3028659 at [http://patimg2.uspto.gov/.piw?Docid=03028659&idkey=NONE US Patent Office] or [https://archive.today/20130124210849/http://wwwpatents.google.com/patents?id=ydtHAAAAEBAJpatent/US3028659 Google]

* View Kilopass Technology Patent US "High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown" Patent #6940751 at [http://patimg2.uspto.gov/.piw?Docid=6940751&idkey=NONE US Patent Office] or [https://archive.today/20130124203754/http://wwwpatents.google.com/patentspatent/about?id=bM0VAAAAEBAJUS6940751 Google]

* View Sidense US "Split Channel Antifuse Array Architecture" Patent #7402855 at [http://patimg2.uspto.gov/.piw?Docid=7402855&idkey=NONE US Patent Office] or [https://archive.today/20130125025213/http://wwwpatents.google.com/patents?id=AYOZAAAAEBAJpatent/US20060244099 Google]

* View the US "Method of Manufacturing Semiconductor Integrated Circuits" Patent #3634929 at [http://patimg2.uspto.gov/.piw?Docid=3634929&idkey=NONE US Patent Office] or [https://archive.today/20130124190255/http://wwwpatents.google.com/patents?id=9MEzAAAAEBAJpatent/US3634929 Google]

* CHOI et al. (2008). [https://wayback.archive-it.org/all/20081031153339/http://www.ee.ucla.edu/~ipl/New_Non-Volatile_Memory_Structures_for_FPGA_Architectures.pdf "New Non-Volatile Memory Structures for FPGA Architectures"]

* For the Advantages and Disadvantages table, see Ramamoorthy, G: "Dataquest Insight: Nonvolatile Memory IP Market, Worldwide, 2008-2013", page 10. Gartner, 2009