Memory controller: Difference between revisions

Revision as of 08:45, 12 June 2024

Revision as of 14:02, 17 June 2024

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Memory controllers contain the logic necessary to read and write to [[dynamic random-access memory]] (DRAM), and to provide the critical [[memory refresh]] and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the [[multiplexer]] circuit, where the [[demultiplexer]] on the DRAM uses the converted inputs to select the correct memory ___location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required [[Bus (computing)|bus]] width for the operation. Memory controllers' bus widths range from [[8-bit]] in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four [[64-bit]] simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a [[128-bit]] memory device.

Some [https://www.icdrex.com memory controllers], such as the one integrated into [[PowerQUICC]] II processors, include [[error detection and correction]] hardware.<ref>[http://www.freescale.com/files/training_pdf/24815_PQ2_MEM_CONTROL_WBT.pdf "Memory Controller"]</ref> A common form of[https://www.icdrex.com| memory controller]] is the [[memory management unit]] (MMU), which in many [[operating system]]s implements [[virtual addressing]]. <!--[[User:Kvng/RTH]]-->

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