AVR microcontrollers: Difference between revisions

Revision as of 18:25, 6 June 2024

Revision as of 14:56, 14 July 2024

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* Navré,<ref>{{cite web|url=http://opencores.org/project,navre|title=Navré AVR clone (8-bit RISC) Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[Verilog]], implements all [[Atmel AVR instruction set|Classic Core]] instructions and is aimed at high performance and low resource usage. It does not support [[interrupt]]s.

* softavrcore,<ref>{{cite web|url=https://opencores.org/projects/softavrcore|title=Soft AVR Core + Interfaces Overview|publisher=OpenCores|access-date=2020-06-16}}</ref> written in [[Verilog]], implements the [[AVR instruction set]] up to AVR5, supports interrupts along with optional automatic interrupt acknowledgement, power saving via [[Idle (CPU)|sleep mode]] plus some peripheral interfaces and [[Hardware_acceleration|hardware accelerators]] (such as [[UART]], [[Serial_Peripheral_Interface|SPI]], [[cyclic redundancy check]] calculation unit and [[Programmable_interval_timer|system timers]]). These peripherals demonstrate how could these be attached to and configured for this core. Within the package, a full-featured [[FreeRTOS]] port is also available as an example for the core + peripheral utilization.

* The opencores project [http://opencores.org/project,cpu_lecture CPU lecture]<ref>{{cite web|url=http://opencores.org/project,cpu_lecture|title=CPU lecture|publisher=OpenCores|access-date=2015-02-16}}</ref> written in [[VHDL]] by Dr. Jürgen Sauermann explains in detail how to design a complete AVR-based [[system on a chip]] (SoC).

== Other vendors ==