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== {{Anchor|SCRAMBLING}}Security ==
A few experimental memory controllers (mostly aimed at the server market where data protection is legally required) contain a second level of address translation, in addition to the first level of address translation performed by the CPU's [[memory management unit]].<ref> Thisto isimprove acache securityand featurebus inperformance.<ref>John thatCarter, itWilson allowsHsieh, theLeigh OperatingStoller, SystemMark toSwansony, provideLixin betterZhang, protectionet separateal. from[http://www.cs.utah.edu/~ald/pubs/hpca99.pdf using"Impulse: Building a bitSmarter toMemory deny arbitrary code execution in (System andController"].</or User) RAM memory areas. ref>
John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al.
[http://www.cs.utah.edu/~ald/pubs/hpca99.pdf "Impulse: Building a Smarter Memory Controller"].
</ref>
Memory controllers integrated into certain [[Intel Core]] processors also provide '''memory scrambling''' as a feature that turns user data written to the main memory into [[pseudo-random]] patterns.<!--apparently this is not considered encryption because it is not cryptographically secure, the main purpose is to avoid current spikes in busses caused by many bits changing in user data simultaneously--><ref>{{cite web
| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-desktop-vol-1-datasheet.pdf
| title = 2nd Generation Intel Core Processor Family Desktop, Intel Pentium Processor Family Desktop, and Intel Celeron Processor Family Desktop
| date = September 2012 | access-date = 2015-11-03
| page = 24
However}}</ref> Memory Scramblingscrambling is supposed to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice, this has not been achieved; Memory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memorymemory Scramblingscrambling Standardsstandards do not fix or prevent security issues or problems . The 2010s Memory Scrambling standardsand are not cryptographically secure, or necessarily open sourced or open to public revision or analysis.<ref>{{cite web ▼}}</ref>
Memory Scrambling (in Cryptographic Theory) is supposed to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice this has not been achieved.
▲However Memory Scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memory Scrambling Standards do not fix or prevent security issues or problems. The 2010s Memory Scrambling standards are not cryptographically secure, or necessarily open sourced or open to public revision or analysis.<ref>{{cite web
| url = http://www.slideshare.net/codeblue_jp/igor-skochinsky-enpub
| title = Secret of Intel Management Engine
}}</ref>
ASUS and Intel have their own memory scrambling standards. Currently ASUS motherboards have allowed the user to choose which memory scrambling standards to use [(ASUS or Intel]) or whether to turn the feature off entirely.
== Variants ==
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