Atmel AVR instruction set: Difference between revisions

Revision as of 19:40, 11 August 2024

Revision as of 01:34, 12 August 2024

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ADD Rd, Rr

ADC Rd, Rr

ADIW Rp+1:Rp, K6

SUB Rd, Rr

SUBI Rdh, K8

SBC Rd, Rr

SBCI Rdh, K8

SBIW Rp+1:Rp, K6

INC Rd

DEC Rd

AND Rd, Rr

ANDI Rdh, K8

OR Rd, Rr

ORI Rdh, K8

<!--

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<S> CLR Rd </S> (EOR)

<S> SER Rdh </S> (LDI)

<S> SBR Rdh, K8 </S> (ORI)

<S> CBR Rdh, K8 </S> (ANDI)

<S> TST Rd </S> (AND)

!-->

SWAPCOM Rd

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COM NEG Rd

NEGCP Rd, Rr

CP CPC Rd, Rr

CPCCPI RdRdh, RrK8

SWAP Rd

CPI Rdh, K8

<!--

SWAP Rd

<S> ROL LSL Rd </S> (ADCADD) !-->

|lang="nasm"|style=font-size:95%}} <!--

<S> LSL ROL Rd </S> (ADDADC) !--><!--

!-->

<S> ROL Rd </S> (ADC) !-->

ROR LSR Rd

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ASR ROR Rd

ASR Rd

LSRMUL Rd, Rr

CPIMULS Rdh, K8Rrh

ROR Rd

MULSU Rdq, Rrq

ASR Rd

FMUL Rdq, Rrq

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FMULS Rdq, Rrq

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FMULSU Rdq, Rrq

MUL Rd, Rr

MULS Rdh, Rrh

MULSU Rdq, Rrq

FMUL Rdq, Rrq

FMULS Rdq, Rrq

FMULSU Rdq, Rrq

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BSET s

BCLR s

SBI IO5, b

CBI IO5, b

BST Rd, b

BLD Rd, b

NOP

BREAK

SLEEP

WDR|lang="nasm"|style=font-size:95%}} <!--

WDR

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MOV Rd, Rr

MOVW Rd+1:Rd, Rr+1:Rr

IN Rd, IO6

OUT IO6, Rr

PUSH Rr

POP Rr

LDI Rdh, K8

LDS Rd, D16

LD Rd, X

LDD Rd, YZ+K6

LD Rd, -XYZ

LD Rd, XYZ+

STS D16, Rr

ST X, Rr

STD YZ+K6, Rr

ST -XYZ, Rr

ST XYZ+, Rr

LPM

LPM Rd, Z

LPM Rd, Z+

ELPM

ELPM Rd, Z

ELPM Rd, Z+

SPM|lang="nasm"|style=font-size:95%}} <!--

SPM

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RJMP S12

IJMP

EIJMP

JMP P22|lang="nasm"|style=font-size:95%}}

JMP P22

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! Call

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RCALL S12

ICALL

EICALL

CALL P22

RET

RETI|lang="nasm"|style=font-size:95%}}

RETI

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! Branch

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CPSE Rd, Rr

SBRC Rr, b

SBRS Rr, b

SBIC IO5, b

SBIS IO5, b

BRBC s, S7

BRBS s, S7|lang="nasm"|style=font-size:95%}}

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