8b/10b encoding: Difference between revisions

Revision as of 03:00, 31 July 2024

Revision as of 19:52, 27 August 2024

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{{Use American English|date = March 2019}}

{{More citations needed|date=January 2015}}

{{Fibre Channel}}

In [[telecommunication]]s, '''8b/10b''' is a [[line code]] that maps [[8-bit]] words to [[10-bit]] [[Symbol (data)|symbol]]s to achieve [[DC bias|DC balance]] and bounded disparity, and at the same time provide enough state changes to allow reasonable [[clock recovery]]. This means that the difference between the counts of ones and zeros in a string of ''at least'' 20 bits is no more than two, and that there are not more than five ones or zeros in a row. This helps to reduce the demand for the lower bandwidth limit of the channel necessary to transfer the signal.<ref>{{Cite journal |journal=IEEE Transactions on Communications |volume=45 |issue=3 |date=March 1997 |title=Performance Assessment of DC-Free Multimode Codes |author=Kees Schouhamer Immink |author-link=Kees Schouhamer Immink |pages=293–299 |doi=10.1109/26.558690 |quote=The ''dc-balanced'' or ''dc-free'' codes, as they are often called, have a long history and their application is certainly not confined to recording practice.}}</ref>

An 8b/10b code can be implemented in various ways with focus on different performance parameters. One implementation was designed by K. Odaka for the [[Digital Audio Tape|DAT]] digital audio recorder.<ref>{{cite patent |country=US |number=4,456,905 |title=Method and apparatus for encoding binary data |pubdate=1984-06-26}}</ref> [[Kees Schouhamer Immink]] designed an 8b/10b code for the [[Digital Compact Cassette|DCC]] audio recorder.<ref>{{cite patent |country=US |number=4,620,311 |title=Method of transmitting information, encoding device for use in the method, and decoding device for use in the method |pubdate=1986-10-28}}</ref> The IBM implementation was described in 1983 by [[Al Widmer]] and [[Peter Franaszek]].<ref>{{cite journal

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* [[CoaXPress]]

* [[Common Public Radio Interface]] (CPRI)

* [[Digital Video Broadcasting|DVB]] [[Asynchronous serial interface]] (ASI)

* [[Digital Visual Interface|DVI]] and [[High-Definition Multimedia Interface|HDMI]] Video Island ([[transition-minimized differential signaling]])

* [[DisplayPort]] 1.x

* [[ESCON]] (Enterprise Systems Connection)

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* [[Open Base Station Architecture Initiative|OBSAI RP3]] interface

* [[PCI Express]] 1.x and 2.x

* [[RapidIO|Serial RapidIO]]

* [[SD UHS-II]]

* [[Serial ATA]]

* [[Serial Attached SCSI|SAS]] 1.x, 2.x and 3.x

* [[Serial Storage Architecture|SSA]]

* [[ServerNet (Tandem)|ServerNet]] (starting with ServerNet2)

* [[SGMII]]

* [[UniPro M-PHY]]<ref>{{cite web|url=http://www.mipi.org/specifications/physical-layer#MPHY |title=Physical Layer Specifications |publisher=MIPI Alliance |work=Mipi.org |access-date=2014-04-20}}</ref>