Memory controller: Difference between revisions

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Some microprocessors in the 1990s, such as the DEC [[Alpha 21066]] and HP [[PA-7300LC]], had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.{{cn|reason=The linked articles do mention a cost motivator but there are no supporting citations.|date=July 2024}}
 
Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM [[POWER8]], which uses external [[Centaur (computing)|Centaur]] chips that are mounted onto [[DIMM]] modules and act as memory buffers, [[L4 cache]] chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.<ref>{{cite web|url=https://www.itjungle.com/2016/10/17/tfh101716-story02/|title=IBM Brings DDR4 Memory To Bear On Power Systems|last=Prickett Morgan|first=Timothy|date=2016-10-17|website=IT Jungle|pages=1|access-date=2017-09-07}}</ref><!--[[User:Kvng/RTH]]-->
 
== Security<span class="anchor" id="SCRAMBLING"></span> ==
== {{Anchor|SCRAMBLING}}Security ==
A few experimental memory controllers contain a second level of address translation, in addition to the first level of address translation performed by the CPU's [[memory management unit]] to improve cache and bus performance.<ref>John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al. [http://www.cs.utah.edu/~ald/pubs/hpca99.pdf "Impulse: Building a Smarter Memory Controller"].</ref>
 
Memory controllers integrated into certain [[Intel Core]] processors provide '''memory scrambling''' as a feature that turns user data written to the main memory into [[pseudo-random]] patterns.<!--apparently this is not considered encryption because it is not cryptographically secure, the main purpose is to avoid current spikes in busses caused by many bits changing in user data simultaneously--><ref>{{cite web
| url = http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-core-desktop-vol-1-datasheet.pdf
| title = 2nd Generation Intel Core Processor Family Desktop, Intel Pentium Processor Family Desktop, and Intel Celeron Processor Family Desktop
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| date = September 2012 | access-date = 2015-11-03
| page = 24
}}</ref> Memory scrambling ishas the supposedpotential to prevent [[Computer forensics|forensic]] and [[reverse-engineering]] analysis based on [[DRAM data remanence]] by effectively rendering various types of [[cold boot attack]]s ineffective. In current practice, this has not been achieved; Memorymemory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s memory scrambling standards do not fix or preventaddress security issues or problems and are not cryptographically secure, or necessarily open sourced or open to public revision or analysis.<ref>{{cite web
| url = http://www.slideshare.net/codeblue_jp/igor-skochinsky-enpub
| title = Secret of Intel Management Engine
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}}</ref>
 
ASUS and Intel have their ownseparate memory scrambling standards. Currently ASUS motherboards have allowed the user to choose which memory scrambling standardsstandard to use (ASUS or Intel) or whether to turn the feature off entirely.{{cn|date=September 2024}}<!--[[User:Kvng/RTH]]-->
 
== Variants ==