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The Intel [[Z170|Z170 chipset]] can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24 MHz instead of the standard 33 MHz.<ref>{{Cite web | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/100-series-chipset-datasheet-vol-1.pdf | title = Intel® 100 Series Chipset Family PCH Datasheet, Vol. 1 | access-date = April 15, 2015}}</ref>
The eSPI bus is also adapted on [[AMD Ryzen]] chipsets.
==Development tools==
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