Serial Peripheral Interface: Difference between revisions

Revision as of 14:04, 28 September 2024

Revision as of 14:17, 28 September 2024

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SPI follows a [[master–slave (technology)|master–slave architecture]], <ref name=":0">{{Cite web |last=Dhaker |first=Piyu |date=2018 |title=Introduction to SPI Interface |url=https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html |url-status=live |archive-url=https://web.archive.org/web/20230525152752/https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html |archive-date=2023-05-25 |access-date=2023-07-21 |website=[[Analog Dialogue]]}}</ref> called ''main–sub'' herein, {{NoteTag|Using main and sub maintains the same initial letters to remain in sync with the line names. For example MISO could be expanded as "main in, sub out"}} {{NoteTag|The {{slink||Alternative terminology}} section gives more details on proposed alternative terminology. See [[Talk:Serial Peripheral Interface#Terminology|the talk page]] for an ongoing discussion.}} where one{{NoteTag|For any given transaction, only one device is the main. However, some devices support changing main and sub roles on the fly. Most microcontrollers can easily reconfigure their SPI's role, and some Atmel and Silabs devices can change roles depending on an external pin.}} main device [[Signaling (telecommunications)|orchestrates communication]] with one or more sub (peripheral) devices by driving the [[clock signal|clock]] and [[chip select]] signals.

[[Motorola]]'s original specification (from the early 1980s) uses four [[Wire|wireslogic signal]]s, aka lines or wires, to performsupport [[full duplex]] communication. It is sometimes called a ''four-wire'' [[serial bus]] to contrast with [[Serial Peripheral Interface#Three-wire|three-wire]] variants which are [[half duplex]], and with the ''two-wire'' [[I²C]] and [[1-Wire]] serial buses.

Typical [[#Applications|applications]] include interfacing [[microcontrollers]] with peripheral chips for [[Secure Digital]] cards, [[liquid crystal display]]s, [[analog-to-digital]] and [[digital-to-analog converters]], [[Flash memory#Serial flash|flash]] and [[EEPROM#Serial bus devices|EEPROM]] memory, and various communication chips.

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[[File:SPI basic operation, single Main & Sub.svg|thumb|368x368px|Figure 1: Common SPI connectivity with a single sub.]]

Commonly, SPI has four [[logic signal]]ssignals. [[#Variations|Variations]] may use different [[#Alternative terminology|names]] or have different signals. Historical terms are shown in parentheses.

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Each device internally uses a [[shift register]] for serial communication, which together forms an inter-chip [[circular buffer]].

Sub devices should use [[tri-state output]]s so their MISO signal becomes [[high impedance]] (electrically disconnected) when the device is not selected. Subs without tri-state outputs cannot share a MISO wireline with other subs without using an external tri-state buffer.

===Data transmission===