Depletion-load NMOS logic: Difference between revisions

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{{See also|NMOS logic#History}}

The original two types of MOSFET logic gates, PMOS and [[NMOS logic|NMOS]], were developed by Frosch and Derick in 1957 at Bell Labs.<ref>{{Cite journal |lastlast1=Frosch |firstfirst1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of Thethe Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref> Following this research, [[Mohamed Atalla|Atalla]] and [[Dawon Kahng|Kahng]] proposed demonstrated a working MOS device with their Bell Labs team in 1960.<ref>{{cite journal |last1=Atalla |first1=M. |author1-link=Mohamed Atalla |last2=Kahng |first2=D. |author2-link=Dawon Kahng |date=1960 |title=Silicon-silicon dioxide field induced surface devices |journal=IRE-AIEE Solid State Device Research Conference}}</ref><ref>{{cite journal |title=1960 – Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/ |journal=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=2023-01-16}}</ref> Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D’Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.<ref>{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5}}</ref> However, the NMOS devices were impractical, and only the PMOS type were practical working devices.<ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |url=https://archive.org/details/historysemicondu00loje_697 |url-access=limited |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=[https://archive.org/details/historysemicondu00loje_697/page/n327 321]–3}}</ref>

In 1965, [[Chih-Tang Sah]], Otto Leistiko and [[Andrew Grove|A.S. Grove]] at [[Fairchild Semiconductor]] fabricated several NMOS devices with channel lengths between [[10 μm process|8{{nbsp}}μm]] and 65{{nbsp}}μm.<ref>{{cite journal |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Leistiko |first2=Otto |last3=Grove |first3=A. S. |title=Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces |journal=[[IEEE Transactions on Electron Devices]] |date=May 1965 |volume=12 |issue=5 |pages=248–254 |doi=10.1109/T-ED.1965.15489 |bibcode=1965ITED...12..248L |url=https://pdfslide.net/documents/electron-and-hole-mobilities-in-inversion-layers-on-thermally-oxidized-silicon-57e531d33262d.html}}</ref> Dale L. Critchlow and [[Robert H. Dennard]] at [[IBM]] also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a [[memory chip]] with 1{{nbsp}}[[kibibit|kb]] data and 50{{ndash}}100 [[nanosecond|ns]] [[access time]], which entered large-scale manufacturing in the early 1970s. This led to MOS [[semiconductor memory]] replacing earlier [[bipolar junction transistor|bipolar]] and [[ferrite-core memory]] technologies in the 1970s.<ref>{{cite journal |last1=Critchlow |first1=D. L. |title=Recollections on MOSFET Scaling |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=1 |pages=19–22 |doi=10.1109/N-SSC.2007.4785536 |doi-access=free }}</ref>