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Stevebroshar (talk | contribs) Though 'wire' is sometimes used, it is less than accurate devices are generally _not_ connected via wire; this is talking about protocol which implies logical signals which are sometimes called lines ... and even wires since their is a separate conductor for each; although probably not a wire ... in particular the link to wire article was misleading |
Undid revision 1239137408 by 193.62.223.115 (talk) saying that one of the edges is "significant" is less informative than saying that the clock idles high or low, especially since the explanation of CPHA refers to the idle level |
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The SPI [[digital timing diagram|timing diagram]] shown is further described below:
* CPOL represents the polarity of the clock. Polarities can be converted with a simple [[inverter (logic gate)|inverter]].
** SCLK{{Subscript|1=CPOL=0}} is a clock
** SCLK{{Subscript|1=CPOL=1}} is a clock
* CPHA represents the [[Phase (waves)|phase]] of each data bit's transmission cycle relative to SCLK.
** For CPHA=0:
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