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== Basic concept ==
=== Background ===
Out-of-order execution is more sophisticated relative to the baseline of in-order execution. In pipelined in-order execution processors, execution of instructions overlap in pipelined fashion with each requiring multiple [[clock cycle]]s to complete. The consequence is that results from a previous instruction will lag behind where they may be needed in the next. In-order execution still has to keep track of these dependencies. Its approach is however quite unsophisticated: stall, every time. Out-of-order uses much more sophisticated data tracking techniques, as described below.
=== In-order processors ===
In earlier processors, the processing of instructions is performed in an [[instruction cycle]] normally consisting of the following steps:
# [[Instruction (computer science)|Instruction]]
# If input [[operand]]s are available (in processor registers, for instance), the instruction is dispatched to the appropriate [[functional unit]]. If one or more operands are unavailable during the current clock cycle (generally because they
# The instruction is executed by the appropriate functional unit.
# The functional unit writes the results back to the [[register file]].<!--[[User:Kvng/RTH]]-->
Often, an in-order processor has a [[bit vector]] recording which registers will be written to by a pipeline.<ref>{{cite web |url=https://pages.cs.wisc.edu/~swilson/gem5-docs/minor.html#sb |title=Inside the Minor CPU model: Scoreboard |author=<!--Not stated--> |date=2017-06-09 |access-date=2023-01-09}}</ref> If any input operands have the corresponding bit set in this vector, the instruction stalls. Essentially, the vector performs a greatly simplified role of protecting against register hazards. Thus out-of-order execution uses 2D matrices whereas in-order execution uses a 1D vector for hazard avoidance.
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