Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 03:22, 16 July 2024

Revision as of 13:22, 7 November 2024

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==Integrated local APICs==

Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[inter-processor interrupt]]s (IPIs) between LAPICs. LAPICsEach one LAPIC may support up to 224 usable [[interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.

All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />

With the introduction of [[Pentium 4 HT]] and [[Pentium D]], each CPU core and each CPU thread are have the integrated LAPIC.

The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com|date=June 2017 }}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>

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==I/O APICs==

I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.<ref name="msi">James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], pp. 10-11</ref> It was packaged as a 64-Pin [[PQFP]].<ref name="i82093AA">{{cite web|url=http://www.intel.com/design/chipsets/datashts/290566.htm|title=Resource & Design Center for Development with Intel|website=Intel}}</ref> The 82093AA normally connected to the [[PIIX3]]/[[PIIX4]] and used its integrated legacy 8259 PICs.<ref name="i82093AA"/> The [[I/O Controller Hub#ICH|ICH1]] and [[Intel 815]] integrated the I/O APIC.

According to a 2009 Intel benchmark using [[Linux]], the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.<ref>James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], p. 19</ref>