Instruction set architecture: Difference between revisions

Revision as of 20:32, 9 November 2024

Revision as of 21:15, 9 November 2024

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*complicated integer and [[floating-point arithmetic]] (e.g. [[square root]], or [[transcendental function]]s such as [[logarithm]], [[sine]], [[cosine]], etc.)

*''{{vanchor|[[Single instruction, multiple data|SIMD]] instruction|SIMD instruction}}s'', a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated [[SIMD register]]s

*performing an atomic [[test-and-set]] instruction or other [[read-modify-writeread–modify–write]] [[atomic instruction]]

*instructions that perform [[arithmetic logic unit|ALU]] operations with an operand from memory rather than a register

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There has been research into [[executable compression]] as a mechanism for improving code density. The mathematics of [[Kolmogorov complexity]] describes the challenges and limits of this.

In practice, code density is also dependent on the [[compiler]]. Most [[optimizing compilerscompiler]]s have options that control whether to optimize code generation for execution speed or for code density. For instance [[GNU Compiler Collection|GCC]] has the option <code>-Os</code> to optimize for small machine code size, and <code>-O3</code> to optimize for execution speed at the cost of larger machine code.

===Representation===

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# Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).

# Other designs employ [[microcode]] routines or tables (or both) to do this, using [[read-only memory|ROMsROM]]s or writable [[random-access memory|RAM]]s ([[writable control store]]), [[programmable logic array|PLAsPLA]]s, or both.

Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the [[Rekursiv]] processor and the [[Imsys]] [[Cjip]]).<ref>{{cite web|url=http://cpushack.net/CPU/cpu7.html |title=Great Microprocessors of the Past and Present (V 13.4.0) |website=cpushack.net |access-date=2014-07-25}}</ref>

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Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the [[instruction pipeline]] only allow a single memory load or memory store per instruction, leading to a [[load–store architecture]] (RISC). For another example, some early ways of implementing the [[instruction pipeline]] led to a [[delay slot]].

The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical [[digital signal processor]] (DSP) must use a kind of [[Harvard architecture]] that can fetch an instruction and two data words simultaneously, and it requires a single-cycle [[multiply–accumulate operation|multiply–accumulate]] [[binary multiplier|multiplier]].

==See also==