Segger Microcontroller Systems: Difference between revisions

Revision as of 02:13, 12 November 2024

Revision as of 02:17, 12 November 2024

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|+ <big>J-Trace & J-Link Models</big><ref>[http://www.segger.com/jlink-model-overview.html J-Link Model Overview; segger.com]</ref>

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! Model !! Host<br/>[[USB#Release_versions|USB]]<br />speed !! Host<br/>[[Ethernet physical layer|Ethernet]]<br />speed !! Host<br/>[[Wi-Fi#Versions_and_generations|Wi-Fi]]<br/>type !! Target<br/>[[volt]]age<br/>range !! Target Trace<br />[[Pin header|connector]]<br />(pins, pitch) !! Target Debug<br/>[[Pin header|connector]]<br />(pins, pitch) !! Target max<br />download<br />speed (max) !! Target<br />[[Virtual COM port|VCOM]]<br />[[Universal asynchronous receiver-transmitter|UART]] !! Segger<br/>software<br/>features !! Photo<br />&nbsp;<br />&nbsp;

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| style="text-align:left" | J-Trace PRO<br/>(''ARM & RISC-V'') || {{yes|3.0 SS}} || {{yes|1 [[Gbit/s]]}} || None || 1.2V to 5V || {{yes|19-pins<br/>(1.27mm)<br/>(150&nbsp;[[MHz]])}} || {{yes|20-pins<br/>(2.54mm)<br/>(50&nbsp;[[MHz]])}} || {{yes|4 [[MByte]]/s}} || 2-pins || All || {{sp}}