Multichannel memory controllers are memory controllers where the DRAM devices are separated onto multiple buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM would be the ideal solution, adding more channels increases complexity and cost.<!--[[User:Kvng/RTH]]-->
=== Fully buffered memory ===
{{Main|Fully Buffered DIMM}}
Fully buffered memory systems place a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fullyfully Bufferedbuffered RAM is used), which unlike traditional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard.<!--[[User:Kvng/RTH]]-->
In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
