Dynamic random-access memory: Difference between revisions

Revision as of 06:55, 26 November 2024

Revision as of 22:04, 26 November 2024

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# At the end of the required amount of time, {{overline|RAS}} must return high.

This can be done by supplying a row address and pulsing {{overline|RAS}} low; it is not necessary to perform any {{overline|CAS}} cycles. An external counter is needed to iterate over the row addresses in turn.<ref name=IBM96>{{cite tech report |type=Application Note |title=Understanding DRAM Operation |date=December 1996 |publisher=[[IBM]] |url=http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|publisher=[[IBM]]|archive-url=https://web.archive.org/web/20170829153054/http://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf|archive-date=29 August 2017|date=December 1996}}</ref> In some designs, the CPU handled RAM refresh, among these the [[Zilog Z80]] is perhaps the best known example, hosting a row counter in a [[processor register]], R, and including internal timers that would periodically poll the row at R and then increment the value in the register. Refreshes were interleaved with common instructions like memory reads.<ref>{{cite book |title=Z80 CPU User Manual |url=http://www.zilog.com/docs/z80/um0080.pdf |page=3}}</ref> In other systems, especially [[home computer]]s, refresh was often handled by the video circuitry as it often had to read from large areas of memory, and performed refreshes as part of these operations.<ref>{{cite web |url=https://retrocomputing.stackexchange.com/questions/14012/what-is-dram-refresh-and-why-is-the-weird-apple-ii-video-memory-layout-affected |title=What is DRAM refresh and why is the weird Apple II video memory layout affected by it? |date=3 March 2020}}</ref>

=====CAS before RAS refresh=====