26-bit computing: Difference between revisions

Revision as of 00:36, 15 December 2024

Latest revision as of 00:37, 15 December 2024

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== History ==

=== IBM System/370 ===

As [[data processing]] needs continued to grow, IBM and their customers faced challenges directly addressing larger memory sizes. In what ended up being a short-term "emergency" solution, a pair of IBM's second wave of System/370 models, the 3033 and 3081, introduced 26-bit real memory addressing, increasing the System/370's amount of physical memory that could be attached by a factor of 4 from the previous [[24-bit computing|24-bit]] limit of 16 MB. IBM referred to 26-bit addressing as "extended real addressing," and some subsequent models also included 26-bit support. However, only 2 years later, IBM introduced [[31-bit computing|31-bit]] memory addressing, expanding both physical and virtual addresses to 31 bits, with its System/370-XA models, and even the popular 3081 was upgradeable to XA standard.

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=== Early ARM processors ===

In the [[ARM_architecture|ARM processor architecture]], 26-bit refers to the design used in the original ARM processors where the [[program counter]] ('''PC''') and [[Status register|Processor Status Register]] ('''PSR''') were combined into one 32-bit [[Processor_registers|register]] (R15), the status flags filling the high 6 bits and the Programprogram Countercounter taking up the lower 26 bits.

In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent [[ARM architecture]]s.

This design enabled more efficient [[Computer_programComputer program|program]] execution, as the Programprogram Countercounter and status flags could be saved and restored with a single operation.{{Citation needed|date=July 2019}} This resulted in faster [[subroutine]] calls and [[interrupt]] response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.

Despite having a [[32-bit computing|32-bit]] ALU and word-length, processors based on ARM architecture version 1 and 2 had only a 26-bit PC and [[address bus]], and were consequently limited to 64 MiB of addressable [[Random Access Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.