Revision as of 09:19, 20 December 2024 edit Guy Harris (talk \| contribs) Extended confirmed users 79,938 edits →APIC timer: Mark that link as "deviated", as per the edit comment for the edit that added the archive link. ← Previous edit		Revision as of 09:20, 20 December 2024 edit undo Guy Harris (talk \| contribs) Extended confirmed users 79,938 edits →Integrated local APICs: ce Next edit →
Line 17: ==Integrated local APICs== Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[inter-processor interrupt]]s (IPIs) between LAPICs. ~~Each~~A ~~one~~single LAPIC may support up to 224 usable [[interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors. All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book\|author=Scott M. Mueller\|title=Upgrading and Repairing PCs\|year=2011\|publisher=Que Publishing\|isbn=978-0-13-268218-3\|page=242\|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)\|P6 processors]] and later ones.<ref name="timer" />

Advanced Programmable Interrupt Controller: Difference between revisions